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TRF7970A
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SLOS743K – AUGUST 2011 – REVISED APRIL 2014
Table 6-41. Supply-Regulator Setting – Automatic 5-V System
Register
00
B7
Option Bits Setting in Control Register
B6 B5 B4 B3 B2 B1
B0
1
5-V system
Action
0B
1
x (1)
0
0
Automatic regulator setting 400-mV difference
(1)
x = don't care
Table 6-42. Supply-Regulator Setting – Automatic 3-V System
Register
00
B7
Option Bits Setting in Control Register
B6 B5 B4 B3 B2 B1
B0
0
3-V system
Action
0B
1
x (1)
0
0
Automatic regulator setting 400-mV difference
(1)
x = don't care
6.14.3.3 Status Registers
6.14.3.3.1 IRQ Status Register (0x0C)
Table 6-43. IRQ Status Register (0x0C)
Function: Information available about TRF7970A IRQ and TX/RX status
Default: 0x00 at POR = H or EN = L, and at each write to the ISO Control Register 0x01. It is also automatically reset at the end of a read
phase. The reset also removes the IRQ flag.
Bit
B7
B6
B5
B4
B3
B2
Name
Irq_tx
Irg_srx
Irq_fifo
Irq_err1
Irq_err2
Irq_err3
Function
IRQ set due to end of TX
IRQ set due to RX start
Signals the FIFO level
CRC error
Parity error
Byte framing or EOF error
Description
Signals that TX is in progress. The flag is set at the start of TX but the interrupt
request (IRQ = 1) is sent when TX is finished.
Signals that RX SOF was received and RX is in progress. The flag is set at the
start of RX but the interrupt request (IRQ = 1) is sent when RX is finished.
Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels (0x14)
register
Indicates receive CRC error only if B7 (no RX CRC) of ISO Control register is
set to 0.
Indicates parity error for ISO14443A
Indicates framing error
Collision error for ISO14443A and ISO15693 single subcarrier. Bit is set if more
B1
Irq_col
Collision error
then 6 or 7 (as defined in register 0x01) are detected inside one bit period of
ISO14443A 106 kbps. Collision error bit can also be triggered by external
noise.
No response within the "No-response time" defined in RX No-response Wait
B0
Irq_noresp
No-response time interrupt
Time register (0x07). Signals the MCU that next slot command can be sent.
Only for ISO15693.
To reset (clear) the register 0x0C and the IRQ line, the register must be read. During Transmit the
decoder is disabled, only bits B5 and B7 can be changed. During Receive only bit B6 can be changed, but
does not trigger the IRQ line immediately. The IRQ signal is set at the end of Transmit and Receive
phase.
Copyright ? 2011–2014, Texas Instruments Incorporated
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